1. Technical Field
The present invention relates to a test apparatus.
2. Related Art
A memory test apparatus includes a fail analysis memory section having therein an address fail memory (AFM) with the same address space as a memory under test. The memory test apparatus compares data read from the memory under test to an expected value, and writes fail data to the corresponding address of the AFM when the comparison result is a mismatch. The memory test apparatus performs a fail repair analysis for the memory under test, based on the fail data in the AFM.
Patent Document 1: Japanese Patent No. 3608694
Patent Document 2: Japanese Patent No. 4241157
The memory test apparatus performs the comparison between the data read from the memory under test and the expected value in units of cells (bits). In contrast, the AFM data is written and read in word units of 16 bits or 32 bits, for example.
Furthermore, there are cases in which the memory test apparatus tests the same cell a plurality of times. In this case, the memory test apparatus writes data indicating a fail to the AFM when this cell is judged to be defective. Even if this cell is judged to be non-defective in later testing, the memory test apparatus does not write data to the AFM indicating that the cell is non-defective, and therefore the information indicating that the cell is defective remains in the AFM.
The memory test apparatus writes fail data for a given cell (bit) at a given address of the memory under test to a bit corresponding to a corresponding address of the AFM, using a read-modify-write process. In this way, the memory test apparatus writes data in bit units to an AFM in which data is read and written word units. Therefore, once a fail judgment is recorded for a given bit, even if the memory test apparatus later judges that the corresponding cell is not defective during later testing, the memory test apparatus still stores a defective judgment for this bit.
However, the operation of writing data to a memory using a read-modify-write process requires an extremely long time. Therefore, when testing the memory under test at high speed, the writing of the fail data to the AFM is too slow.
To solve this problem, a memory test apparatus is known that includes a fail analysis memory section in which a plurality of AFMs are arranged in parallel corresponding to a single memory under test. This memory test apparatus sequentially selects one of the AFMs at a time in an interleaved manner and writes the fail data to the selected one AFM. This memory test apparatus can increase the speed at which the fail data is written from the perspective of the fail analysis memory section. Therefore, this memory test apparatus can prevent the writing of the fail data to the AFMs from being too slow.
However, with this memory test apparatus, a large number of AFMs must be mounted. Accordingly, with this memory test apparatus, the apparatus is large and the cost is high.